FPGA and Verification Design Solutions

       BDS offers a complete FPGA design and verification solution including Architecture and Partitioning, Timing, RTL coding, IP Cores, Test Bench generation, and verification with emphasis on performance and integration.

FPGA Design Solutions

• Xilinx Virtex2, Virtex2Pro, Virtex4, Altera, Actel, Lattice
• IP Cores, CoreGen, Custom IP
• Gigabit Ethernet, SONET, TDM, and IPv4 Processing
• High Seed Memory and Bus Interfaces/Exchangers
• Compact Flash, Video Display interfaces
• Data Processing for DSP Applications
• Packet Monitoring, Classification, and Modification
• Packet/TDM Processor Design
• Mappers/Framers Interface Design
• High-speed Interface Design (SPI3, SPI4.2, PCI)

FPGA Verification Solutions

• Random and Directed Tests
• Chip Verification, Network Processor Modeling, and System Modeling
• TCL, Verilog, and C Test Benches
• Modelsim, VERA, VCS
• C, C++, and SystemC
• Code Coverage Tools